This application claims the benefit of Korean Patent Application No. 1999-48738, filed on Nov. 5, 1999, which is hereby incorporated by reference for all purposes as if fully set forth herein.
1. Field of the Invention
The present invention relates to a driving circuit for an active matrix display, and more particularly to a shift register for driving a pixel array that is adapted to prevent a short of a capacitor.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) with an active matrix driving system uses thin film transistors (TFTs) as a switching device to display a natural moving picture. Such an LCD has been widely used for a monitor for a personal computer or a notebook computer as well as office automation equipment such as copying machines, etc., and portable equipment such as cellular phones and pagers, etc.
The active matrix LCD includes a gate driving circuit for sequentially applying a scanning pulse to row lines connected to gate electrodes of TFTs to sequentially scan a pixel train for each row line. This gate driving circuit consists of a plurality of shift registers connected in cascade to sequentially generate a scanning pulse in response to a start pulse.
Referring to FIG. 1, the conventional shift register includes n stages 21 to 2n connected to a start pulse input line. Output lines 41 to 4n of the n stages 21 to 2n are connected to n row lines ROW1 to ROWn included in a pixel array, respectively. A scanning pulse SP is applied to the first stage 21, and output signals g1 to gnxe2x88x921 of the first to (nxe2x88x921)th stages are applied to the respective subsequent stages as scanning pulses. The input signals of the shift register, that is, the scanning pulse, first to fourth clock signals C1 to C4 having a phase delayed sequentially, the supply voltage VDD and the ground voltage VSS, are applied from external sources. As shown in FIG. 2, each of the stages 21 to 2n includes: a first NMOS transistor T1 connected between a first node P1 and a fourth node P4; a second NMOS transistor T2 connected between the first node P1, a second node P2 and a ground voltage line 10; a third NMOS transistor T3 connected between a supply voltage line 8, a third clock signal line 6c and the second node P2; a fourth NMOS transistor T4 connected between the second node P2, the fourth node P4, and the ground voltage line 10; a first capacitor CP1 connected between the first node P1 and an output line 4i; a fifth NMOS transistor T5 connected between the first clock signal line 6a and the output line 4i; and a sixth NMOS transistor T6 connected between the second node P2, the output line 4i and the ground voltage line 10.
When the (ixe2x88x921)th row line input signal gixe2x88x921 having a high level is applied from the previous stage 2ixe2x88x921, the first and fourth NMOS transistors T1 and T4 are turned on. Then, a voltage at the first node P1 goes to a high level by the supply voltage VDD applied upon turning-on of the first NMOS transistor T1, whereas a voltage at the second node P2 is discharged to the ground voltage line 10 upon turning-on of the fourth NMOS transistor T4, so as to have a low level. As can be seen from FIG. 3, the third clock signal C3 remains at a low level voltage in a time interval when the (ixe2x88x921)th row line input signal gixe2x88x921 has a high level voltage. In other words, a high-level voltage region of the third clock signal C3 does not overlap with that of (ixe2x88x921)th row line input signal gixe2x88x921. Thus, the third and fourth NMOS transistors T3 and T4 are not turned on at the same time, so that a voltage at the second node P2 is determined independently of a channel width ratio (or resistance ratio) of the third NMOS transistor T3 to the fourth NMOS transistor T4. Accordingly, even though element characteristics of the third and fourth NMOS transistors T3 and T4 are non-uniform, a circuit characteristic of the shift register is not changed to such a large extent that a normal operation is impossible. Also, since the third and fourth NMOS transistors T3 and T4 are not turned on at the same time, an overcurrent does not flow in the third and fourth NMOS transistors T3 and T4. As a result, not only are the element characteristics of the third and fourth NMOS transistors T3 and T4 not deteriorated, but also the power consumption is reduced.
If a high level voltage emerges at the first node P1, then the fifth NMOS transistor T5 is turned on. In this state, the output line 4i begins to discharge the first clock signal C1 passing through the source and drain of the fifth NMOS transistor T5 when the first clock signal C1 has a high level voltage. Thus, a high level voltage emerges at the output line 4i. When a high level voltage of first clock signal C1 is applied to the output line 4i, the capacitor CP1 raises a voltage at the first node P1 by the voltage level of the first clock signal C1. As the gate voltage is increased by the capacitor CP1, the fifth NMOS transistor T5 delivers the high-level first clock signal C1 into the output line 4i rapidly without any attenuation. Accordingly, a voltage loss caused by a threshold voltage of the fifth NMOS transistor T5 is minimized.
Subsequently, if the first clock signal C1 is changed from a high level voltage to a low level voltage, then an output voltage Vout at the output line 4i also is changed from a high level voltage to a low level voltage. This results from the fifth NMOS transistor T5 being in a turned-on state due to a voltage at the first node P1.
Next, if the third clock signal C3 is changed from a low level voltage to a high level voltage, then the third NMOS transistor T3 is turned on and hence a voltage at the second node P2 has a high level. The second NMOS transistor T2 also is turned on by virtue of a high level voltage at the second node P2 applied to its gate to discharge a voltage at the first node P1 into a ground voltage source VSS connected to the ground voltage line 10. Likewise, the sixth NMOS transistor T6 also discharges a voltage at the output line 4i, via the ground voltage line 10, into the ground voltage source VSS by virtue of a high level voltage at the second node P2 applied to its gate. As a result, a voltage at the first node P1 and then output voltage at the output line 4i have a low level.
Meanwhile, when the first clock signal C1 input to the drain of the fifth NMOS transistor T5 changes from a low level voltage to a high level voltage in such a state that a voltage at the first node P1 remains at a high level, the voltage at the first node P1 rises. In this case, a voltage rise width )Vp at the first node P1 can be set accurately by the first capacitor CP1 connected between the first node P1 and the output node 4i and a capacitor CP 12 provided between the first node P1 and the ground voltage line 10. The voltage rise width )Vp at the first node P1 is given by the following equation:                               Δ          ⁢                      xe2x80x83                    ⁢          Vp                =                                            CP1              +                              C                OX                                                    CP12              +              CP1              +                              C                OX                                              ⁢          Δ          ⁢                      xe2x80x83                    ⁢          Vout                                    (        1        )            
wherein Cox represents a parasitic capacitance of the fifth NMOS transistor T5. Capacitance values of the capacitors CP1 and CP12 can be set to about 0.1 to 10 pF.
The capacitor CP2 connected between the second node P2 and the ground voltage line 10 restrains a voltage variation at the second node P2 when the output voltage Vout at the output node 4i changes and, at the same time, restrains a voltage variation at the second node P2 caused by a leakage current from the NMOS transistors.
Since the capacitors CP1, CP2 and CP12 are used for the purpose of reducing a voltage drop caused by an element leakage current and a voltage variation at the first and second nodes P1 and P2 caused by a coupling effect, the shift resister does not malfunction even when the capacitors CP1, C2 and CP12 do not exist. Also, even though capacitance values of the capacitors CP1, CP2 and CP12 is changed to some degree, the shift register can operate almost normally. However, if any one of the capacitors CP1, CP2 and CP12 has a short circuit, then the shift register malfunctions and hence fails to generate a normal scanning pulse. For instance, the capacitors CP1, CP2 and CP12 have a short circuit when silicon particles or pin holes are mingled in the process of forming an insulating film using the vapor deposition technique. Since the capacitors CP1, CP2 and CP12 are designed to have a relatively large size, for example, since they have a size of about 100 xcexcmxc3x97100 xcexcm when capacitance values of the capacitors CP1, CP2 and CP12 are about 1 pF, the probability of particles or pin holes mingling into the insulating film becomes high.
If the capacitor CP1 connected between the first node P1 and the output line 4i has a short, then the first NMOS transistor T1 fails to charge the output voltage sufficiently because the first node P1 is connected in series to the output line 4i, increasing the load. Further, if the capacitor CP1 has a short, then a scanning pulse applied to the next stage fails to have a normal voltage level because a bootstrap of the first node P1 is not made, reducing the magnitude of an output pulse applied to the output line 4i. When the second capacitor CP2 connected between the second node P2 and the ground voltage line 10 has a short, the second node P2 is connected, in series, to the ground voltage line 10 to set the voltage at the second node P2 to the ground voltage potential, VSS. As a result, a voltage charged into the first node P1 can not be discharged to always maintain a turned-on state of the fifth transistor T5, so that an output voltage emerging at the output line 4i becomes equal to the first clock signal C1. If the capacitor CP12 connected between the first node P1 and the ground voltage line 10 has a short, then a voltage at the first node P1 is fixed to the ground voltage potential, VSS. As a result, the fifth NMOS transistor T5 always maintains an off state to keep an output voltage emerging at the output line 41 in a floating state or at a low level.
Accordingly, the present invention is directed to a shift register that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a shift register that is adapted to prevent a short of a capacitor, and/or a problem caused by such a short.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a shift register according to an embodiment of the present invention has a plurality of stages each of which comprises an output circuit including a pull-up transistor having a first input electrode for receiving a first clock signal, a first output electrode connected to a row line and a first control electrode, and a pull-down transistor having a second input electrode connected to a low-level voltage source, a second output electrode connected to the row line and a second control electrode; an input circuit for generating a first control signal to be applied to the first control electrode and for generating a second control signal to be applied to the second control electrode in response to a second clock signal having a phase different from the first clock signal; and a first capacitor connected between the input circuit and the row line, a second capacitor connected between the second control electrode and the low-level voltage source and a third capacitor connected between the first control electrode and the low-level voltage source, at least one of the first to third capacitors having at least two capacitors connected in series.
A shift register according to another embodiment of the present invention has a plurality of stages each of which comprises an output circuit including a pull-up transistor having a first input electrode for receiving a first clock signal, a first output electrode connected to a row line and a first control electrode, and a pull-down transistor having a second input electrode connected to a low-level voltage source, a second output electrode connected to the row line and a second control electrode; an input circuit for generating a first control signal to be applied to the first control electrode and for generating a second control signal to be applied to the second control electrode in response to a second clock signal having a phase different from the first clock signal; and a first capacitor connected between the input circuit and the row line, a second capacitor connected between the second control electrode and the low-level voltage source, a third capacitor connected between the first control electrode and the low-level voltage source, and a fourth capacitor connected between the first capacitor and the input circuit, at least one of the first to fourth capacitors having at least two capacitors connected in series.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.